The present invention relates to testing of integrated circuits, and more particularly, to reducing peak power during transition fault testing of integrated circuits.
Transition fault testing is an important test performed during the design phase of an integrated circuit (IC) and is used to identify and locate signal transition faults. Transition fault testing usually is performed at the rated clock speed to test the response of the IC and is also known as an at-speed test. At-speed tests can be performed as scan tests. Scan tests involve selecting a trace path in the IC for testing. During a scan test, an input signal is provided to a pin in the trace path. The signal then propagates through the trace path and a value of the signal is read at a destination pin. The value is examined to determine if the two pins are properly connected in the trace path.
The test signals used in scan tests may not always adhere to the functional characteristics of the IC. In other words, the test signals may cause the IC to operate in states that are non-functional or not-reachable, resulting in high switching activity. The high switching activity uses high power and requires high peak currents, which in turn lead to excessive voltage or current-resistive (IR) drops. As a result, logic elements in the IC receive less voltage leading to signal propagation delays. The above-mentioned limitations can cause ICs to fail the at-speed scan tests. Also, the power dissipation due to high peak currents may cause permanent damage or hot-spots in the IC. Hence, it is important to keep the switching activity in scan tests close to the switching activity that occurs during the functional operation of the IC.
Many solutions have been proposed to address the problem of high switching caused by scan tests. One solution involves segmenting the IC into scan chains and enabling one scan chain at a time to capture the test response. A scan chain refers to digital logic elements (flip-flops, latches, registers, etc.) that receive the same gated clock signal. Another solution is known as functional scan testing and involves restricting the states of the IC to operational/functional states in a capture cycle. However, identifying the operational states of a large, complex IC is a very difficult task.
Yet another solution that has been proposed to reduce high switching activity is shown in FIG. 1. FIG. 1 is a schematic diagram of a conventional circuit for performing transition fault testing of an integrated circuit (IC) 100. The IC 100 includes a clock gating cell 102 and a scan chain 103. The scan chain 103 includes flip-flops 105 and 107. The clock gating cell 102 is used for gating a clock signal to the flip-flops 105 and 107. The IC 100 may include many such scan chains and clock gating cells. The clock gating cell 102 controls the clock signal to the flip-flops 105 and 107. The clock gating cell 102 includes a test enable (TE) port 109, an enable (E) port 111 and a clock input 113 for receiving the clock signal. Each of the flip-flops 105 and 107 include an input port “D” 115, a scan enable (SE) port 117, a scan data input (SDI) port 119 and a clock input 121 for receiving a clock signal. An output port 122 of the flip-flop 107 is connected to the SDI port 119 of the flip-flop 105. The TE port 109 is connected to the SE port 117 and receives the SE signal, which is also received at the SE port 117 of the flip-flops 105 and 107. An output port “Q” 123 of the clock gating cell 102 is connected to the clock input 121 of the flip-flops 105 and 107.
In launch on capture (LoC) transition tests, the SE signal remains asserted during the scan shift operation and de-asserted during the scan capture operation. The timing diagrams for the SE signal for the scan shift and scan capture operations in LoC transition tests are shown in FIG. 2. In launch on scan (LoS) transition tests, the SE signal remains asserted during the scan shift operation until the end of the first capture cycle and de-asserted during the remaining capture operation. The timing diagrams for the SE signal for the scan shift and scan capture operations in LoS transition tests are shown in FIG. 3.
In an LoC test, the SE signal at the TE port 109 remains asserted (for positive logic, at logic “1”) during the scan shift operation and de-asserted during the scan capture operation. During the scan shift operation, when the SE signal at the TE port 109 is high, the clock gating cell 102 provides the clock signal to each of the flip-flops 105 and 107. During the scan capture operation, the SE signal at the TE port remains de-asserted, resulting in the clock gating cell 102 providing the clock signal to the flop-flops 105 and 107 depending on a functional enable signal 125. The functional enable signal 125 is received at the “E” port 111 from functional logic 127. The functional logic 127 is used to enable and disable the clock to the flip-flops 105 and 107 in the functional mode. In scan mode, the functional enable signal 125 from the functional logic 127 is used to control the clock to the flip-flops 105 and 107 during the capture operation. The clock signal is selectively supplied to the flip-flops 105 and 107 depending on the functional enable signal 125. As a result, the peak power of the IC 100 is less than that when there is no clock gating.
However, in an LoS transition test, high peak power still is used by the IC 100. In the LoS transition test, the SE signal at the TE port 109 remains asserted during the scan shift operation and the first cycle of the scan capture operation. The SE signal at the TE port 109 is the same as the SE signal shown in FIG. 3. Since the SE signal at the TE port 109 stays high for the first capture cycle, each of the flip-flops 105 and 107 receives the clock signal, resulting in the IC 100 having high peak power.
Therefore, there is a need for a way to reduce the peak power during transition fault testing (both for LoC and LoS transition tests).